Publications

 

Editorials, Books, and Book Chapters

  1. H. Asadi, P. Ienne, and H. Sarbazi-Azad, “Guest Editors’ Introduction: Architecture of Future Many Core Processors”, Elsevier’s Microprocessors and Microsystems Journal, To Appear, 2017.
  2. H. Asadi, P. Ienne, and H. Sarbazi-Azad, “Guest Editors’ Introduction: Special Issue on Emerging Memory Technologies in Very Large Scale Computing and Storage Systems”, IEEE Transactions on Computers,Vol. 65, Issue 4, 2016.
  3. M. Jamzad, A. Movaghar, and H. Asadi (Editors), “Artificial Intelligence and Signal Processing”, Springer Cham Heidelberg, Communications in Computer and Information Science Series, Vol. 427, Oct. 2014.
  4. A.H. Jahangir, A. Movaghar, and H. Asadi (Editors), “Computer Networks and Distributed Systems”, Springer Cham Heidelberg, Communications in Computer and Information Science Series, Vol. 428, Oct. 2014.

Published / Accepted Journal Papers

  1. Z. Ebrahimi, B. Khaleghi, and H. Asadi, “PEAF: A Power-Efficient Architecture for SRAM-Based FPGAs Using Reconfigurable Hard Logic Design in Dark Silicon Era,” IEEE Transactions on Computers (TC), Special Section on Innovation in Reconfigurable Computing Fabrics: from Devices to Architectures, In press, 2017.
  2. S. Yazdanshenas, B. Khaleghi, P. Ienne, and H. Asadi, “Designing Low Power and Durable Digital Blocks Using Shadow Nano-Electromechanical Relays,” IEEE Transactions on Very Large Scale Integration Systems (TVLSI), In press, 2017.
  3. H. Farbeh, N.S. Mirzadeh, N. Farhady, S.G. Miremadi, M. Fazeli, and H. Asadi, “A Cache-Assisted ScratchPad Memory for Multiple Bit Error Protection,” IEEE Transactions on Very Large Scale Integration Systems (TVLSI), Vol. 24, Issue 11, Nov. 2016.
  4. M. Ebrahimi, H. Asadi, R. Bishnoi, and M. B. Tahoori, “Layout-based Modeling and Mitigation of Multiple Event Transients,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), Vol. 35, No. 3, March 2016.
  5. M. M. Tarihi, H. Asadi, A. Haghdoost, M. Arjomand, and H. Sarbazi-Azad, “A Hybrid Non-Volatile Cache Design for Solid-State Drives Using Comprehensive I/O Characterization,” IEEE Transactions on Computers (TC), Vol. 65, Issue 6, 2016.
  6. S. Yazdanshenas, H. Asadi, and B. Khaleghi, “A Scalable Dependability Scheme for Routing Fabric of SRAM-Based Reconfigurable Devices“, IEEE Transactions on Very Large Scale Integration Systems (TVLSI), Vol. 23, No. 9, September 2015.
  7. S. Alinezhad, Z. Delavari, H. Asadi, and S. G. Miremadi, “On Endurance and Performance of Erasure Codes in SSD-based Storage Systems,”  Elsevier  Microelectronics Reliability (MR), Vol. 55, 2015.
  8. M. Tarihi, H. Asadi, and H. Sarbazi-Azad, “DiskAccel: Accelerating Disk-Based Experiments by Representative Sampling“, ACM Performance Evaluation Review (Special Issue on ACM SIGMETRICS-2015 Conference),  Vol. 43, Issue 1, June 2015.
  9. R. Salkhordeh, H. Asadi, and S. Ebrahimi, “Operating System Level Data Tiering Using Online Workload Characterization,” Journal of Supercomputing, 2015.
  10. B. Khaleghi, H. Asadi, A. Ahari, and S. Bayat-Sarmadi, “FPGA-based Protection Scheme against Hardware Trojan Horse Insertion Using Dummy Logic,” IEEE Embedded Systems Letters, Vol. 7, No. 2, 2015.
  11. S. Yazdanshenas and H. Asadi, “Fine-Grained Architecture in Dark Silicon Era for SRAM-Based Reconfigurable Devices,” IEEE Transactions on Circuits and Systems II, Vol. 61, Issue 10, Oct. 2014.
  12. S. Rezaei, S.G. Miremadi, H. Asadi, and M. Fazeli, “Soft Error Estimation and Mitigation of Digital Circuits by Characterizing Input Patterns of Logic Gates,” Elsevier Microelectronics Reliability, Vol. 54, Issue 6-7, June-July 2014.
  13. H. Asadi, A. Haghdoost, M. Ramezani, N. Elyasi, and A. Baniasadi, “CEDAR: Modeling Impact of Component Error Derating and Read Frequency on System-Level Vulnerability in High-Performance Processors”, Elsevier Microelectronics Reliability, Vol. 54, Issue 5, May 2014.
  14. F. Rajaei Salmasi, H. Asadi, and M. GhasemiGol, “Impact of Stripe Unit Size on Performance and Endurance of SSD-Based RAID Arrays“, Scientia Iranica, Transactions D, Vol. 20, No 6, pp. 1978-1998, Dec. 2013.
  15. Z. Ghaderi, S.G. Miremadi, H. Asadi, and M. Fazeli, “HAFTA: Highly Available Fault-Tolerant Architecture to Protect SRAM-Based Reconfigurable Devices against Multiple Bit Upsets”, IEEE Transactions on Device and Materials Reliability (TDMR), Vol. 13, Issue 1, March 2013.
  16. M. Ebrahimi, S.G. Miremadi, H. Asadi, and M. Fazeli, “A Low Cost Scan Chain-Based Technique to Recover Multiple Errors in TMR Systems”, IEEE Transactions on Very Large Scale Integration Systems (TVLSI), Vol. 21, Issue 8, Aug. 2013.
  17. H. Asadi and M. B. Tahoori, M. Fazeli, and S.G. Miremadi, “Efficient Algorithms to Accurately Compute Derating Factors of Digital Circuits,” Elsevier Microelectronics Reliability, Vol. 52, No. 6, June 2012.
  18. H. Asadi and M.B. Tahoori, “Soft Error Modeling and Remediation Techniques in ASIC Designs,” Elsevier Journal of Microelectronics Engineering, Vo. 41, No. 8, Aug. 2010.
  19. M.B. Tahoori, H. Asadi, B. Mullins, and D. Kaeli, “Obtaining FPGA Soft Error Rate in High Performance Information Systems,” Elsevier Microelectronics Reliability, Volume 49, Issue 5, May 2009.
  20. H. Asadi, M.B. Tahoori, B. Mullins, D. Kaeli, and K. Granlund, “Soft Error Susceptibility Analysis of SRAM-Based FPGAs in High-Performance Information Systems,” IEEE Transactions on Nuclear Science (TNS), December 2007.
  21. H. Asadi and M.B. Tahoori, “Analytical Techniques for Soft Error Rate Modeling and Mitigation of FPGA-Based Designs”, IEEE Transactions on Very Large Scale Integration Systems (TVLSI), December 2007.
  22. H. Asadi, A.R. Ejlali, and S.G. Miremadi, “Fast Co-Verification of HDL Models,” Elsevier Journal of Microelectronic Engineering, Vol. 48, Issue 2, pp. 218-228, Feb. 2007.
  23. V. Sridharan, H. Asadi, M. B. Tahoori, and D. Kaeli, “Reducing Data Cache Susceptibility to Soft Errors,” IEEE Transactions on Dependable and Secure Computing (TDSC), Nov.-Dec. 2006.

Rigorously Refereed Conference Papers (Acceptance Rate: 10% ~ 40%)

  1. Z. Seifoori, B. Khaleghi, and H. Asadi, “A Power Gating Switch Box Architecture in Routing Network of SRAM-Based FPGAs in Dark Silicon Era,” IEEE/ACM Design, Automation and Test in Europe Conference (DATE), Lausanne, Switzerland, March 2017.
  2. M. Kishani, R. Eftekhari, and H. Asadi, “Evaluating Impact of Human Errors on the Availability of Data Storage Systems,” IEEE/ACM Design, Automation and Test in Europe Conference (DATE), Lausanne, Switzerland, March 2017.
  3. B. Khaleghi, B. Omidi, H. Amrouch, J. Henkel, and H. Asadi, “Stress-Aware Routing to Mitigate Aging Effects in SRAM-based FPGAs,” 26th International Conference on Field Programmable Logic and Applications (FPL), Lausanne, Switzerland, Sep. 2016.
  4. Reza Salkhordeh and H. Asadi, “An Operating System Level Data Migration Scheme in Hybrid DRAM-NVM Memory Architecture,” IEEE/ACM Design, Automation and Test in Europe Conference (DATE), Dresden, Germany, March 2016.
  5. I. Ahmadpour, B. Khaleghi, and H. Asadi, “An Efficient Reconfigurable Architecture by Characterizing Most Frequent Logic Functions,” 25th International Conference on Field Programmable Logic and Applications (FPL), London, UK, Sep. 2015.
  6. M. Tarihi, H. Asadi, and H. Sarbazi-Azad, “DiskAccel: Accelerating Disk-Based Experiments by Representative Sampling“, ACM SIGMETRICS, Portland, Oregon, June 2015 (*Proceedings will be published in a special issue by ACM Performance Evaluation Review; **Also listed in the journal papers).
  7. A. Ahari, H. Asadi, B. Khaleghi, Z. Ebrahimi, and M. B. Tahoori, “Towards Dark Silicon Era in FPGAs Using Complementary Hard Logic Design,” 24th International Conference on Field Programmable Logic and Applications (FPL), Munich, Germany, Sep. 2014.
  8. A. Ahari, H. Asadi, and M. Tahoori, “Emerging Non-Volatile Memory Technologies for Future Low Power Reconfigurable System”,  International Symposium on Reconfigurable Communication-centric Systems-on-Chip (ReCoSoC), Montpellier, France, May 2014 (Invited Paper).
  9. A. Ahari, H. Asadi, B. Khaleghi, and M. B. Tahoori, “A Power-Efficient Reconfigurable Architecture Using PCM Configuration Technology,” IEEE/ACM Design, Automation and Test in Europe Conference (DATE’14), Dresden, Germany, March 2014.
  10. S. Alinezhad, S.G. Miremadi, and H. Asadi “On Endurance of Erasure Codes in SSD-Based Storage Systems,” 17th CSI International Symposium on Computer Architecture & Digital Systems (CADS), Tehran, Oct. 2013.
  11. A.M Hosseini Monazzah, H. Farbeh, S.G. Miremadi, M. Fazeli, and H. Asadi, “FTSPM: A Fault-Tolerant ScratchPad Memory,” IEEE/IFIP Intl. Conf. on Dependable Systems and Networks (DSN), Budapest, Hungary, June 2013.
  12. M. Ebrahimi, H. Asadi, M.B. Tahoori, “A Layout-based Approach for Multiple Event Transient Analysis,” 50th Design Automation Conference (DAC), Austin, TX, June 2013.
  13. M. H. Hajkazemi, A. Baniasadi, and H. Asadi, “FARHAD: a Fault-Tolerant Power-Aware Hybrid Adder for Add Intensive Applications,” 24th IEEE International Conference on Application-specific Systems, Architectures and Processors (ASAP), Washington D.C., June 2013.
  14. M. Ebrahimi, L. Chen, H. Asadi, M.B. Tahoori, “CLASS: Combined Logic and Architectural Soft Error Sensitivity Analysis”, 18th Asia and South Pacific Design Automation Conference (ASP-DAC), Yokohama, Japan, Jan. 2013.
  15. M. Fazeli, S.N. Ahmadian, S.G. Miremadi, H. Asadi, and M. B. Tahoori, “Soft Error Rate Estimation of Digital Circuits in the Presence of Multiple Event Transients (METs)”, IEEE/ACM Design, Automation and Test in Europe Conference (DATE’11), France, March 2011.
  16. M. Ebrahimi, S.G. Miremadi, and H. Asadi, “ScTMR: A Scan Chain-Based Error Recovery Technique for TMR Systems in Safety-Critical Applications”, IEEE/ACM Design, Automation and Test in Europe Conference (DATE’11), France, March 2011.
  17. A. Haghdoost, A. Baniasadi, and H. Asadi, “System-Level Vulnerability Estimation for Cache Memories,” 16th IEEE Pacific Rim International Symposium on Dependable Computing (PRDC’10), Tokyo, Japan, Dec. 2010.
  18. M. Fazeli, S.G. Miremadi, H. Asadi, and S.N. Ahmadian, “A Fast and Accurate Multi-Cycle Soft Error Rate Estimation Approach to Resilient Embedded Systems Design”, IEEE/IFIP Intl. Conf. on Dependable Systems and Networks, (DSN-2010), Chicago, USA, 2010.
  19. A. Haghdoost, H. Asadi, and A. Baniasadi, “Using Input-to-Output Masking for System-Level Vulnerability Estimation in High-Performance Processors,” The 15th CSI Intl. Conf. on Computer Architecture & Digital Systems (CADS), Tehran, Sept. 2010, (Best Paper Award).
  20. M. Fazeli, S.G. Miremadi, H. Asadi, and M. B. Tahoori, “A Fast Analytical Approach to Multi-Cycle Soft Error Rate Estimation of Sequential Circuits”, 13th EUROMICRO Conference on Digital System Design, Lille, France, Sept. 2010.
  21. H. Asadi, A. Haghdoost, and R. Eftekhari, “Availability Impact of Hard and Soft Failures in Enterprise Storage Systems,” Fast Abstract in IEEE/IFIP Intl. Conf. on Dependable Systems and Networks (DSN-2010), Chicago, USA, 2010.
  22. H. Asadi, and M. B. Tahoori, and C. Tirumurti, “Estimating Error Propagation Probabilities with Bounded Variances,” IEEE Intl. Symp. On Defect and Fault Tolerance in VLSI Systems (DFT), Rome, Italy, Sept. 2007.
  23. B. Mullins, H. Asadi, M.B. Tahoori, D. Kaeli, K. Granlund, and R. Bauer, “Case Study: Soft Error Rate Analysis in Storage Systems”, IEEE VLSI Test Symp. (VTS07), Berkeley, CA, May 2007.
  24. H. Asadi and M.B. Tahoori, “Soft Error Derating Computation in Sequential Circuits”, IEEE/ACM Intl. Conference on Computer Aided Design (ICCAD), San Jose, CA, November 2006.
  25. H. Asadi and M. B. Tahoori, “Soft Error Hardening for Logic-Level Designs”, IEEE Intl. Symp. on Circuits and Systems (ISCAS), Kos, Greece, May 2006.
  26. H. Asadi, V. Sridharan, M. B. Tahoori, and D. Kaeli, “Vulnerability Analysis of L2 Cache Elements to Single Event Upsets,” IEEE/ACM Design, Automation and Test in Europe Conference (DATE’06), Germany, March 2006.
  27. H. Asadi, V. Sridharan, M. B. Tahoori, and D. Kaeli, “Reliability Tradeoffs in Design of Cache Memories,” Workshop on Architectural Reliability (WAR-1), held in conj. with MICRO-38, Barcelona, Spain, Nov. 2005.
  28. H. Asadi and M. B. Tahoori, “Soft Error Modeling and Protection for Sequential Elements”, IEEE Intl. Symp. On Defect and Fault Tolerance in VLSI Systems (DFT), pp. 463-471, Monterey, CA, Oct. 2005.
  29. H. Asadi and M. B. Tahoori, “Soft Error Mitigation for SRAM-Based FPGAs,” IEEE VLSI Test Symp. (VTS05), Palm Springs, CA, May 2005.
  30. H. Asadi and M. B. Tahoori, “An Analytical Approach for Soft Error Rate Estimation in Digital Circuits,” IEEE Intl. Symp. on Circuits and Systems (ISCAS), pp. 2991-2994, Kobe, Japan, May 2005.
  31. H. Asadi, V. Sridharan, M. B. Tahoori, and D. Kaeli, “Balancing Reliability and Performance in the Memory Hierarchy,” IEEE Intl. Symp. on Performance Analysis of Systems and Software (ISPASS05), Austin, Texas, March 2005.
  32. H. Asadi and M. B. Tahoori, “An Accurate SER Estimation Method Based on Propagation Probability,” IEEE/ACM Design, Automation and Test in Europe Conference (DATE’05), March 2005.
  33. H. Asadi and M. B. Tahoori, “Soft Error Rate Estimation and Mitigation for SRAM-Based FPGAs,” ACM Intl. Symp. on Field-Programmable Gate Arrays (FPGA-2005) , Monterey,  CA, Feb. 2005.
  34. H. Asadi, S.G. Miremadi, H.R. Zarandi, and A.R. Ejlali, “Evaluation of Fault-Tolerant Designs implemented on SRAM-Based FPGAs,” IEEE/IFIP Pacific Rim Intl. Symp. on Dependable Computing (PRDC2004), Papeete, Tahiti, March, 2004.
  35. A.R. Ejlali, S.G. Miremadi, H.R. Zarandi, H. Asadi, and S. Sarmadi, “A Hybrid Fault Injection Approach Based on Simulation and Emulation Co-operation,” IEEE/IFIP Intl. Conf. on Dependable Systems and Networks, (DSN-2003), San Francisco, June 2003.
  36. H. Asadi, S.G. Miremadi, H.R. Zarandi, and A.R. Ejlali, “Fault Injection into SRAM-Based FPGAs for the Analysis of SEU Effects,” IEEE Intl. Conference on Field programmable Technology (FPT-2003), pp. 428-430, Tokyo, Japan, December 2003.
  37. S. Sarmadi, S.G. Miremadi, H. Asadi, and A. R. Ejlali, “Fast Prototyping with Co-Operation of Simulation and Emulation,” Lecture Notes in Computer Science (LNCS), Springer-Verlag [12th Intl. Conf. on Field Programmable Logic and Applications (FPL-2002)], Vol. 2438, M. Glesner & P. Zipf (Eds), Springer 2002.
  38. S.G. Miremadi, S. Sarmadi, and H. Asadi, “Speedup Analysis in Simulation-Emulation Co-Operation,” IEEE Intl. Conference on Field programmable Technology (FPT’02), pp. 394-398, Hong Kong, Dec 2002.

Other Publications

  1. B. Mullins, H. Asadi, M.B. Tahoori, D. Kaeli, “Soft Error Rate Analysis in Storage Systems”, IEEE Boston Area Architecture (BARC) Workshop, Jan. 2007.
  2. H. Asadi and M. B. Tahoori, “Timing-Logic Derating Computation Using Event Propagation Probabilities”, 2nd Workshop on System Effects o Logic Soft Errors (SELSE 2), Urbana-Champaign, IL, April 2006.
  3. H. Asadi and M. Hashempour, “Hardening Techniques in CMOS Combinational Logic”, IEEE 14th North Atlantic Test Workshop (NATW05), Essex Junction, VT, May 2005.
  4. H. Asadi, V. Sridharan, M. B. Tahoori, and D. Kaeli, “Balancing Reliability and Performance in the Memory Hierarchy,” IEEE Boston Area Architecture (BARC) Workshop, Feb. 2005.
  5. H. Asadi and S.G. Miremadi, “Co-Verification of Partially Synthesizable Models,” IEEE 13th North Atlantic Test Workshop (NATW04), pp. 71-78, Essex Junction, VT, May 2004.
  6. H. Asadi and M. B. Tahoori, “An Analytical Approach for Soft Error Rate Estimation of SRAM-Based FPGAs,” MAPLD04 Conference, Washington DC, September 2004.
  7. S. Hessabi, A. Ahmadinia, H. Asadi, S. Sarmadi, and M. Gudarzi, “Co-FFT Design: FFT Implementation on CSoC,” IEEE-TTTC Intl. Conference on Automation, Quality and Testing, Robotics (AQTR-2002), pp. 312-317, Romania, May 2002.
  8. H. Asadi, S.G. Miremadi, S. Sarmadi, and A. R. Ejlali, “Speeding up Design Verification Using Co-Operation of Simulation and Emulation,” IEEE-TTTC Intl. Conf. on Automation, Quality and Testing, Robotics (AQTR-2002), Romania, 2002.